TY  - RPRT
TI  - Optimization of heuristic logic synthesis by iteratively reducing circuit substructures using a database of optimal implementations
AU  - Tran, A. P.
AU  - Jatkar, D. D.
AU  - Ali Al-Radhawi, M.
AU  - Ernst, E. A.
AU  - Sontag, E. D.
PY  - 2025
DO  - 10.1101/2025.11.28.691216
UR  - https://www.biorxiv.org/content/10.1101/2025.11.28.691216v1
ID  - 10.1101/2025.11.28.691216
ER  -